1. Field of the Invention
The present invention relates to a clock jitter calculation device for calculating the magnitude of clock jitter in a semiconductor integrated circuit caused by power source noise, or the like, with which it is possible to, for example, perform timing analysis and timing verification with clock jitter taken into consideration.
2. Description of the Background Art
With finer process rules, the influence from the physical phenomena, such as crosstalk, electromigration, hot-carrier degradation, and power source voltage drop (IR drop), has become pronounced, affecting the operation of semiconductor integrated circuits. The power source voltage drop, among others, has become particularly pronounced as the process rules become finer. This is a phenomenon that occurs due to the resistance of the power source line in a circuit, and is influenced by simultaneous switching of a plurality of circuits. A significant voltage drop decreases the operation speed of the circuit, and may lead to an erroneous operation of the circuit.
Conventionally, countermeasures have been taken, such as performing timing verification with a design margin taken into account, and reinforcing the power source line based on a reduction in the clock transmission delay and/or based on empirical rules. However, these countermeasures increase the chip area and the power consumption due to excessive designing, in addition to increasing the man-hour for design. In view of this, Japanese Laid-Open Patent Publication No. 10-321725, for example, proposes a timing verification method using a cell library storing the cell delay time for each supply voltage. In this method, the lowest supply voltage of each cell is estimated based on the switching information of the cell, and the delay time of the cell is obtained according to the estimated lowest supply voltage of the cell. Then, timing verification is performed based on the delay time of each cell thus obtained.
However, with the timing verification method in which the delay time is determined according to the lowest supply voltage as described above, it is not possible to perform the analysis for circuits for which jitter guarantees are required (e.g., fast IF (interface) circuits and AD (analog/digital) converters). Moreover, for some paths of which timing is analyzed (extending from the start point of analysis to the end point of analysis), there is often obtained an analysis result with a timing margin or a verification result with no timing margin.
However, recent system LSIs, for example, which have an increased degree of integration, an increased speed and a decreased operating voltage, are more significantly influenced by jitter of a clock signal being transmitted. Therefore, the conventional method, in which the influence of jitter of a clock signal being transmitted cannot be taken into consideration, tends to produce less reliable verification results. Thus, there is an increased possibility that an actual device will operate erroneously even if timing verification indicates a normal operation. In worst cases, the device may need to be re-designed, thus imposing a significant risk.
These problems mentioned above become even more pronounced when the process rule rapidly becomes finer or when the functionality of a system LSI is increased. Thus, in order to improve the performance and the reliability of a chip, it is important to accurately determine, control and reduce the magnitude of clock jitter.